Processor chip timing adjustment enhancement
US12406119B2 · kind B2 · utility
0Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2021 |
| Grant date | Sep 2, 2025 |
| Priority date | — |
| Expiry date | Dec 31, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Data relating to one or more circuit paths may be collected during a design stage of a processor chip based on a design model. One or more delta values may be added to the one or more circuit paths of the design model. One or more broken circuit paths may be identified based on the one or more delta values. A target time for each of the one or more broken circuit paths may be adjusted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.