Methods of forming microelectronic devices, and related microelectronic devices, memory devices, and electronic systems
US12406728B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2022 |
| Grant date | Sep 2, 2025 |
| Priority date | — |
| Expiry date | Feb 21, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microelectronic device includes a stack structure, slot structures, and dielectric material. The stack structure includes blocks each including a vertically alternating sequence of conductive material and insulative material arranged in tiers. At least one of the blocks includes an array region including strings of memory cells, and a staircase region including a crest sub-region interposed between a staircase structure and the array region. An uppermost boundary of the tiers within the crest sub-region underlies an uppermost boundary of the tiers within the array region. The slot structures are interposed between the blocks of the stack structure. The dielectric material extends over and between the blocks of the stack structure. A thickness of a portion of the dielectric material overlying the crest sub-region is greater than a thickness of an additional portion of the dielectric material overlying the array region. Related memory devices, electronic systems, and methods are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.