Memory device with multi-layered charge storage stack
US12408342B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2022 |
| Grant date | Sep 2, 2025 |
| Priority date | — |
| Expiry date | Jan 10, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
Abstract
An integrated circuit structure includes a plurality of gate layers, a laterally stacked multi-layered memory structure, and a vertical channel layer. The gate layers laterally extend above the substrate and spaced apart from each other. The laterally stacked multi-layered memory structure extends upwardly above the substrate and through the gate layers and including a blocking layer, a charge storage stack, and a tunneling layer. The charge storage stack is on the blocking layer and including a first silicon nitride layer, a second silicon nitride layer, and a silicon oxynitride layer sandwiched between the first and second silicon nitride layers. The tunneling layer is on the charge storage stack. The vertical channel layer is on the laterally stacked multi-layered memory structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.