Method of reducing program disturbance in memory device and memory device utilizing same

US12412609B2 · kind B2 · utility

Assignee

• YANGTZE MEMORY TECHNOLOGIES CO., LTD. · CN

Inventors

• Shan Li · 红钢城街道, CN
• Kaikai You · 红钢城街道, CN
• Ying Cui · 红钢城街道, CN
• Jianquan Jia · 红钢城街道, CN
• Kaiwei Li · 红钢城街道, CN
• An Zhang · Kunshan, CN

Key dates

• Filing date: Apr 25, 2023
• Grant date: Sep 9, 2025
• Expiry date: Dec 21, 2043

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C16/24
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

In some aspects, a memory device is provided. The memory device includes a plurality of memory strings and a peripheral circuit. One of the memory strings includes memory cells, a select transistor coupled to a select line and a bit line, and a dummy cell coupled to a dummy word line and arranged between the select transistor and the memory cells. The peripheral circuit is coupled to the memory strings and configured to, in a pre-pulse period of a program operation, maintain a first voltage on the select line to retain an on-state of the select transistor and apply a second voltage to the dummy word line to turn off the dummy cell. After applying the second voltage to the dummy word line, the peripheral circuit is further configured to apply a third voltage to the select line to turn off the select transistor.