Methods for forming three-dimensional memory devices
US12412628B2 · kind B2 · utility
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7References
20Claims
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Key dates
| Filing date | May 20, 2024 |
| Grant date | Sep 9, 2025 |
| Priority date | — |
| Expiry date | May 20, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for forming a three-dimensional (3D) memory device is disclosed. An array of NAND memory strings is formed on a first substrate. A first semiconductor layer is formed above the array of NAND memory strings. The first semiconductor layer includes single crystalline silicon. A first transistor is formed on the first semiconductor layer. A second semiconductor layer is formed above the first transistor. The second semiconductor layer includes single crystalline silicon. A second transistor is formed on the second semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.