Manufacturing method of package structure
US12414243B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2022 |
| Grant date | Sep 9, 2025 |
| Priority date | — |
| Expiry date | Feb 26, 2044 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing package structure includes following steps. An insulating composite layer is formed on a metal layer of a carrier board. A chip packaging module including a sealant and a first chip embedded therein is disposed on the insulating composite layer, in which the first chip has a plurality of conductive pads. A first circuit layer module including a dielectric layer and a circuit layer is formed on the chip packaging module, in which the circuit layer is on the dielectric layer and electrically connected to the conductive pads through a conductive vias in the dielectric layer. A second chip is disposed on the first circuit layer module. A second circuit layer module is formed on the first circuit layer module and the second chip. A protecting layer is formed on the second circuit layer module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.