Modified read counter incrementing scheme in a memory sub-system
US12417035B2 · kind B2 · utility
0Cited by
3References
18Claims
0Family size
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Key dates
| Filing date | Jan 23, 2024 |
| Grant date | Sep 16, 2025 |
| Priority date | — |
| Expiry date | Jan 23, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a memory device including multiple memory cells and a processing device operatively coupled to the memory device. The processing device is to receive a first read command at a first time. The processing device is further to receive a second read command at a second time. The processing device is further to determine that the first read command and the second read command are directed to an at least partially same set of memory cells of the plurality of memory cells. The processing device is further to perform a media management operation with respect to the at least partially same set of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.