Integrated circuit structures having backside gate tie-down

US12419085B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Leonard P. GULER · Hillsboro, US
• Mauro J. Kobrinsky · Portland, US
• Mohit K. HARAN · Hillsboro, US
• Marni Nabors · Portland, US
• Tahir Ghani · Portland, US
• Charles H. Wallace · Portland, US
• Allen B. Gardiner · Portland, US
• Sukru YEMENICIOGLU · Portland, US

Key dates

• Filing date: Mar 30, 2022
• Grant date: Sep 16, 2025
• Expiry date: Jan 18, 2044

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0151
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

Integrated circuit structures having backside gate tie-down are described. In an example, a structure includes a first vertical stack of horizontal nanowires over a first sub-fin, and a second vertical stack of horizontal nanowires over a second sub-fin, the second vertical stack of horizontal nanowires spaced apart from and parallel with the first vertical stack of horizontal nanowires. A gate structure includes a first gate structure portion over the first vertical stack of horizontal nanowires, wherein the first gate structure extends along an entirety of the first sub-fin. A second gate structure portion is over the second vertical stack of horizontal nanowires, wherein the second gate structure does not extend along an entirety of the second sub-fin. A gate cut is between the first gate structure portion and the second gate structure portion.