Buried metal signal rail for memory arrays

US12424550B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Biswanath Senapati · Mechanicville, US
• Seiji Munetoh · Tokyo, JP
• Nicholas Anthony Lanzillo · Wynantskill, US
• Lawrence A. Clevenger · Saratoga Springs, US
• Geoffrey Burr · Cupertino, US
• Kohji Hosokawa · South Burlington, US

Key dates

• Filing date: Sep 6, 2022
• Grant date: Sep 23, 2025
• Expiry date: Jan 21, 2044

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N70/231
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An IC memory device includes a substrate and an array of memory cells on the substrate. Each memory cell includes at least one memory cell transistor in a layer of the device adjacent to the substrate. In the same layer, the device also includes a plurality of shunt transistors. The device also includes a buried metal signal rail, which is disposed between the array of memory cells and the plurality of shunt transistors in a buried layer that is embedded into the substrate below the transistors. The device also includes single-layer vias, which are in same layer as the transistors and electrically connect the memory cell transistors to the shunt transistors through the buried metal signal rail.