Self-aligning interconnect for a digital system
US12425014B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2024 |
| Grant date | Sep 23, 2025 |
| Priority date | — |
| Expiry date | Mar 15, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K21/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) chip includes transmit circuitry including multiple transmitters to launch parallel data in response to a transmit clock signal. The transmit clock signal is based on a reference clock signal. Receiver circuitry includes multiple receivers to receive the parallel data in response to a receive clock signal. The receive clock signal is based on the reference clock signal. Bus circuitry includes multiple data paths arranged in parallel between the transmit circuitry and the receiver circuitry. Each data path is coupled between a given one of the multiple transmitters and a given one of the multiple receivers. A first data path of the multiple data paths includes a delay circuit to dynamically delay first data of the parallel data propagating along the first data path by a first delay that is based on a channel delay exhibited by a second data path of the multiple data paths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.