Low germanium, high boron silicon rich capping layer for PMOS contact resistance thermal stability

US12426342B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Debaleena Nandi · Hillsboro, US
• Cory Bomberger · Portland, US
• Gilbert Dewey · Beaverton, US
• Anand S. Murthy · Beaverton, US
• Mauro J. Kobrinsky · Portland, US
• Rushabh SHAH · Hillsboro, US
• Chi-Hing Choi · Portland, US
• Harold W. Kennel · Portland, US
• Omair Saadat · Beaverton, US
• Adedapo A. Oni · North Plains, US
• Nazila Haratipour · Hillsboro, US
• Tahir Ghani · Portland, US

Key dates

• Filing date: Jun 25, 2021
• Grant date: Sep 23, 2025
• Expiry date: Dec 5, 2043

Classification

• Technology area (CPC B): Performing Operations; Transporting
• CPC primary: B82Y10/00
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

Embodiments disclosed herein include semiconductor devices with improved contact resistances. In an embodiment, a semiconductor device comprises a semiconductor channel, a gate stack over the semiconductor channel, a source region on a first end of the semiconductor channel, a drain region on a second end of the semiconductor channel, and contacts over the source region and the drain region. In an embodiment, the contacts comprise a silicon germanium layer, an interface layer over the silicon germanium layer, and a titanium layer over the interface layer.