Multi-processor bridge with cache allocate awareness
US12430201B2 · kind B2 · utility
0Cited by
10References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2024 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Feb 14, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/657
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for loading data, comprising receiving a memory management command to perform a memory management operation to load data into the cache memory before execution of an instruction that requests the data, formatting the memory management command into one or more instruction for a cache controller associated with the cache memory, and outputting an instruction to the cache controller to load the data into the cache memory based on the memory management command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.