Metal gate structure and method of forming the same
US12431356B2 · kind B2 · utility
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10References
20Claims
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Key dates
| Filing date | Jun 4, 2022 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Nov 20, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/667
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device includes forming a gate trench over a semiconductor substrate, depositing a gate dielectric layer and a work function layer in the gate trench, depositing a capping layer over the work function layer, passivating a surface portion of the capping layer to form a passivation layer, removing the passivation layer, depositing a fill layer in the gate trench, recessing the fill layer and the capping layer, and forming a contact metal layer above the capping layer in the gate trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.