Vertical transistor, integrated circuitry, method of forming a vertical transistor, and method of forming integrated circuitry

US12432928B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Hung-Wei Liu · Jinshanmian, TW
• Vassil Antonov · Boise, US
• Ashonita A. Chavan · Boise, US
• Darwin Franseda Fan · Boise, US
• Jeffery B. Hull · Boise, US
• Anish A. Khandekar · Boise, US
• Masihhur R. Laskar · Boise, US
• Albert Liao · Boise, US
• Xue-Feng Lin · Boise, US
• Manuj Nahar · Boise, US
• Irina Vasilyeva · Boise, US

Key dates

• Filing date: Nov 29, 2023
• Grant date: Sep 30, 2025
• Expiry date: Apr 5, 2044

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/05
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.