Post gate dielectric processing for semiconductor device fabrication
US12433011B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2023 |
| Grant date | Sep 30, 2025 |
| Priority date | — |
| Expiry date | Dec 14, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.