Method for fabrication of integrated circuit structure with full dielectric isolation utilizing selective oxidation
US3944447A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 1973 |
| Grant date | Mar 16, 1976 |
| Priority date | — |
| Expiry date | Mar 12, 1993 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/928
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Structure: An integrated circuit structure with full dielectric isolation comprising a supporting substrate having a planar surface of dielectric material and a semiconductor layer on said dielectric surface which forms a planar interface with the surface. Regions of oxidized silicon extend through the layer from said interface, surrounding and dielectrically isolating pockets of silicon in the layer; the oxidized silicon regions extend to the upper surface of the semiconductor layer where they are substantially co-planar with the silicon pockets. The devices of the integrated circuit are formed in said silicon pockets. Method: The structure is fabricated by a novel method wherein a lightly doped silicon layer is deposited on a highly doped silicon substrate; surrounding oxidized silicon regions are then formed by selectively thermally oxidizing portions of the silicon layer to form oxide regions which are co-extensive with the oxidized areas and, thus, are co-planar with the remaining silicon pockets at both surfaces of the layer; a member having a dielectric surface interfacing with the silicon layer is formed, and the silicon substrate is removed by preferential electrochemical …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.