High performance integrated bipolar and complementary field effect transistors
US4016596A · kind A · utility
18Cited by
3References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 26, 1976 |
| Grant date | Apr 5, 1977 |
| Priority date | — |
| Expiry date | Jan 26, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/615
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating both bipolar as well as complementary MOS field effect transistors, i.e., BI-CMOS transistors in the same semiconductor substrate. The preferred embodiment of the method provides bipolar and CMOS transistors having breakdown voltages (BV.sub.ceo) in excess of 10 volts and CMOS devices having no latchup problems, with a minimum number of processing steps. The method also contemplates the formation of auxiliary devices such as resistors and Schottky Barrier diodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.