Integrated circuit chip carrier and method for forming the same
US4023197A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 1975 |
| Grant date | May 10, 1977 |
| Priority date | — |
| Expiry date | Jun 25, 1995 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit chip carrier with multi-level metallurgy, in which the effects of the metallurgy in causing elevation irregularities at the various levels of the structure are minimized, is produced by a method wherein a first plurality of levels of metallization patterns respectively separated by layers of dielectric material are first formed on a planar primary layer supported on a temporary substrate having a chemical etchability different from that of the layer. The primary layer is electrically insulative with respect to said metallization patterns. Then, a supporting layer is formed on the uppermost covering layer, after which the substrate is removed with a chemical etchant which preferentially etches the substrate away from the insulative layer. Next, an opposite plurality of levels of metallization patterns are formed on the side of the insulative layer opposite to the first formed metallization patterns. These opposite metallization patterns are also respectively separated by covering layers of dielectric material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.