Method of propagation delay testing a level sensitive array logic system
US4063080A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1976 |
| Grant date | Dec 13, 1977 |
| Priority date | — |
| Expiry date | Jun 30, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Propagation delay testing is performed on a generalized and modular logic system that contains embedded arrays and can be used as arithmetic/logical/control unit in a digital computer or data processing system. Each such unit can be composed of combinatorial logic and storage circuitry. The storage circuitry may be of two types, randomly arranged latches, or arrays of storage cells. In the organization presented here the latches are arranged such that they have the capability of performing scan-in/scan-out operations independently of system control. Using this scan capability, the method of the invention provides for the state of the storage latches to be preconditioned and independent of prior circuit history. Selected propagation paths are sensitized by patterns from an automated test generator or designer supplied patterns. By alternating selected inputs and by applying proper timing control, propagation delay indications through the selected paths are obtained to determine delay behavior of the logic system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.