Reduced overhead for clock testing in a level system scan design (LSSD) system
US4071902A · kind A · utility
19Cited by
2References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1976 |
| Grant date | Jan 31, 1978 |
| Priority date | — |
| Expiry date | Jun 30, 1996 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318533
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The disclosure relates to LSSD systems for use in digital computers and the like. More particularly, to an organization of logic in such systems to render the clock networks testable with minimal overhead. The advantages of the practice of the invention are particularly apparent and enhanced when the invention is employed in a Level Sensitive Scan Design (LSSD) System generally of the type disclosed in U.S. Pat. No. 3,783,254 and U.S. patent application Ser. No. 701,052, filed June 30, 1976.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.