Method of level sensitive testing a functional logic system with embedded array
US4074851A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1976 |
| Grant date | Feb 21, 1978 |
| Priority date | — |
| Expiry date | Jun 30, 1996 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Level sensitive testing is performed on a generalized and modular logic with embedded array system that is utilized as an arithmetic/logical unit in a digital computer. Each arithmetic/logical unit of a computer is formed of arrangements of combinational logic networks, arrays and storage circuitry. The storage circuitry has the capability for performing scan-in/scan-out operations independently of the system input/output and controls. Using the scan capability, the method of the invention provides for the state of the storage circuitry to be preconditioned and independent of its prior history. Test patterns from an automatic test generator are cycled through the networks of combinational logic and arrays and their respective associated storage circuitry for removal through the scan arrangement to determine their fault status.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.