Method for making a silicon mask
US4256532A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 1978 |
| Grant date | Mar 17, 1981 |
| Priority date | — |
| Expiry date | Dec 4, 1998 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24479
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In the fabrication of semiconductor integrated circuits, a method is provided for forming a self-supporting silicon mask and a further method is provided for utiliziing such a self-supporting separable silicon mask to perform various masking steps in the integrated circuit fabrication. The mask is formed by forming, at a surface of a planar silicon substrate, a silicon layer having a higher concentration of conductivity-determining impurities than the substrate beneath the layer, applying to selected portions of the other surface of the substrate an etchant which preferentially etches silicon having lower concentrations of conductivity-determining impurities to thus etch out preferentially selected portions of the substrate to form at least one recess extending through the substrate to said silicon layer, and then etching from the surface of said silicon layer opposite the substrate recess to form patterns of openings extending through the silicon layer to said substrate recess. The seperable self-supporting silicon mask thus formed is then placed on the surface of an integrated semiconductor circuit member so that the opposite surface of the silicon layer interfaces with the integ…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.