Level sensitive scan design (LSSD) system
US4293919A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 1979 |
| Grant date | Oct 6, 1981 |
| Priority date | — |
| Expiry date | Aug 13, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318583
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
One of the significant features of the invention, as in U.S. Pat. No. 3,783,254, is the implementation of shift register latches as basic building blocks in a logic organization and system with combinational logic networks which provide the excitation for the shift register latches. These shift register latches in the invention as well as in the patent contain a pair of latches where one is a "master" latch and another a "slave". The structure in the patent requires the "master" and "slave" latches to be part of the shift register for scan-in/scan-out. However, only the "master" may be set with data from the logic system surrounding it while the "slave" may only be set with data which previously resided in the related "master" latch. Thus, in those logic organizations where only the "master" latch output is required, the usefulness of the "slave" latch is limited to scan-in/scan-out. In the shift register latch of the invention, the "slave" latch must be set with the data that resided in the related "master" latch during scan-in/scan-out. However, in logic systems requiring the use of only one latch of the shift register latch, both "master" and "slave" latches can perform independ…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.