Process for dislocation-free slot isolations in device fabrication
US4456501A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1983 |
| Grant date | Jun 26, 1984 |
| Priority date | — |
| Expiry date | Dec 22, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3065
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor wafer masked with a masking layer having an opening therethrough exposing a portion of the wafer which is to be etched to form a depression of a desired depth is etched via a first plasma etching step under high bias voltage-high energy conditions with a plasma which includes chlorine and a shape modifier species, e.g., argon, to a first depth which is less than the desired depth. Thereafter, the depression is treated by a second plasma etching step under low bias voltage-low energy plasma etching conditions with a plasma which includes chlorine and is substantially free of the shape modifier species. A wet chemical etch follows to remove damaged silicon and impurities. The resulting depression has relatively straight walls and is relatively free of cusps and apexes. The depression is formed quickly and has a desired shape while only a minimal amount of damage and impurities are introduced into the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.