Double planarization process for multilayer metallization of integrated circuit structures
US4481070A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 1984 |
| Grant date | Nov 6, 1984 |
| Priority date | — |
| Expiry date | Apr 4, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76819
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process is disclosed for the planarization of an integrated circuit structure by a two stage planarization process which comprises: applying over a metallization layer, having one or more openings therein, a layer of insulation sufficiently thin to avoid formation of voids in the portion of the insulation applied in the openings in the metallization layer; smoothing the insulation layer by removing the high portions of the insulation by, for example, dry etching the insulation; applying a further layer of insulation over the first insulation layer; and smoothing the further layer of insulation by removing the high portions by, for example, dry etching; whereby the resultant smoothed insulation surface will be substantially planar and substantially void-free. In a preferred embodiment, a second material, such as a photoresist material, is coated over the insulation layer prior to the smoothing step, particularly when an anisotropic dry etching process is used, to insure that only the high portions of the insulation layer are removed in the etching step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.