Method of manufacturing high capacity semiconductor capacitance devices
US4507159A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 7, 1981 |
| Grant date | Mar 26, 1985 |
| Priority date | — |
| Expiry date | Oct 7, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/64
Abstract
The present invention provides for a method for manufacturing a charge storage region in a semiconductor substrate for a memory cell in a dynamic RAM, comprising forming an insulating layer on the substrate, forming a masking layer over the insulating layer, forming at least one aperture in the masking layer, the aperture defining the charge storage region in the semiconductor substrate, implanting dopant ions of a first polarity through the aperture for diffusion through the substrate, and implanting dopant ions of a second polarity through the aperture for diffusion through the substrate to a lesser degree than the first polarity dopant diffusion so that the diffusion of the first polarity dopant with respect to the diffusion of the second polarity dopant forms a P-N junction substantially aligned with the edge of the masking layer aperture to define the periphery of the charge storage region. One way of diffusing the second polarity dopant to a lesser degree than the first polarity dopant in the substrate is to select a first polarity dopant which has a diffusivity greater than the second polarity dopant. Another way of achieving the desired diffusion of first polarity dopant wi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.