Method of concurrently testing each of a plurality of interconnected integrated circuit chips
US4509008A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 1984 |
| Grant date | Apr 2, 1985 |
| Priority date | — |
| Expiry date | Apr 10, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318583
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed is a design discipline, or approach, in the form of circuitry and a test method, or methodology which obviates the problems of the prior art and allows testing of each individual chip and interchip connections of a plurality of interconnected chips contained on or within a high density packaging structure. This testing is accomplished without the need for and utilization of test equipment having a precision probe and a high precision step and repeat mechanism. CPA is a method and circuit design discipline that, where followed, will result in a testable multichip package given that each logical component is testable and the design is synchronous in nature. The CPA discipline is able to accomplish this by making use of shift register latches on the chips or functional island periphery. These latches are used to indirectly observe and/or control the synchronous network, in many ways replicating the stuckfault test environment under which tests were generated at the lower subcomponent level of assembly. One method, full CPA, offers the ability to apply these tests to all full CPA chips on the multichip package simultaneously or in unison, thus reducing manufacturing tester ti…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.