Raised split gate EFET and circuitry
US4574208A · kind A · utility
23Cited by
6References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 21, 1982 |
| Grant date | Mar 4, 1986 |
| Priority date | — |
| Expiry date | Jun 21, 2002 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/914
Abstract
Lateral FET structure is disclosed for bi-directional power switching. A raised gate structure enables distal gate electrode portions to be in close proximity to FET channels and the remainder of the gate to be separated from the drift or drain region by a substantially greater distance so as to prevent undesired inducement of potential conduction channels through the drift region in the OFF state. This enables the gate to be referenced to the same potential level as one of the main terminals in the OFF state while still affording high voltage blocking capability. A multicell matrix array is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.