Process for manufacturing an integrated circuit with tantalum silicide connections utilizing self-aligned oxidation
US4593454A · kind A · utility
55Cited by
8References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 20, 1984 |
| Grant date | Jun 10, 1986 |
| Priority date | — |
| Expiry date | Nov 20, 2004 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/147
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention concerns an integrated circuit the monocrystalline or polycrystalline silicon zones of which the source, gate and drain are covered with tantalum silicide TaSi.sub.2 while the remainder of the slice is covered with portions of a layer of tantalum oxide Ta.sub.2 O.sub.5, especially on the sides of the grids of polycrystalline silicon and on the thick oxide and an aluminum alloy layer comes into contact with the tantalum silicide to form connections with the portions of tantalum silicide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.