Method of fabricating silicon-on-insulator transistors with a shared element
US4649627A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 1984 |
| Grant date | Mar 17, 1987 |
| Priority date | — |
| Expiry date | Jun 28, 2004 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/164
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a shared element semiconductor structure in which the insulating layer of a silicon-on-insulator structure is patterned to form a gate oxide. The bulk semiconductor underlying the insulating layer is defined into an FET (field-effect transistor) with its gate region below the gate oxide. The epitaxial layer above the insulating layer is defined into another FET with its drain region above the gate oxide, whereby the drain region also operates as the gate electrode for the bulk FET. Also described is a method of forming a silicon on insulator substrate with insulating layer usable as a gate oxide by means of bonding a silicon substrate to an oxidized epitaxial layer on another silicon seed substrate and then removing the seed substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.