Semiconductor memory having multiple level storage structure
US4661929A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 24, 1984 |
| Grant date | Apr 28, 1987 |
| Priority date | — |
| Expiry date | Dec 24, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a semiconductor memory includes a memory array consisting of a plurality of memory cells respectively having at least one storage capacitor, an addressing circuit which designates location of each memory cell, data lines which transmit data connected to said memory cells and data writing and reading circuits connected to said data lines. The semiconductor memory has a multiple level storage structure. In particular, the memory includes an arrangement for sequentially applying, on a time series basis, different voltages of at least 3 levels or more to the gate of a switching MOS transistor of said memory cells, a bias charge supplying means as said data reading circuit and a column register providing at least two or more storage cells which temporarily store said data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.