Semiconductor memory having circuit effecting refresh on variable cycles
US4672586A · kind A · utility
35Cited by
3References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 6, 1984 |
| Grant date | Jun 9, 1987 |
| Priority date | — |
| Expiry date | Jun 6, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4074
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory using a dynamic memory device, wherein a battery supplies a power source voltage and a substrate bias voltage when the memory is cut off from an external device, and a refresh control circuit changes in refresh timing of the memory device in accordance with the leakage current of the memory device. The power consumption of the memory can thus be reduced and the data can be kept for an extended period without an external power source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.