Method of making a planar structure containing MOS and bipolar transistors
US4707456A · kind A · utility
25Cited by
4References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 18, 1985 |
| Grant date | Nov 17, 1987 |
| Priority date | — |
| Expiry date | Sep 18, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/401
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A highly planarized integrated circuit structure having at least one bipolar device and at least one MOS device is described as well as a method of making the structure. The structure comprises a substrate having a field oxide grown thereon with portions defined therein respectively for formation of a collector region and a base/emitter region for a bipolar device and a source/gate/drain region for an MOS device. All of the contacts of the devices are formed using polysilicon which fills the defined portions in the field oxide resulting in the highly planarized structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.