Semiconductor memory using multiple level storage structure
US4709350A · kind A · utility
41Cited by
2References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 5, 1984 |
| Grant date | Nov 24, 1987 |
| Priority date | — |
| Expiry date | Jul 5, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a semiconductor memory for reading and writing of stored charge in an X-Y address system by arranging a plurality of memory cells each including a capacitance element and one MOS-FET in matrix, this invention discloses a semiconductor memory using multiple level storage structure for read and write of at least more than two multi-level data stored in the capacitance elements, by applying a multi-level step voltage to the plate electrode of the capacitance or to the gate electrode of MOS-FET so as to write and read signal charge.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.