Plugged poly silicon resistor load for static random access memory cells
US4727045A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 1986 |
| Grant date | Feb 23, 1988 |
| Priority date | — |
| Expiry date | Jul 30, 2006 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved process for fabricating a static RAM cell having a polysilicon load resistance is provided. Following formation of source, gate and drain regions, a planarized dielectric structure is formed over the junction regions, and via openings which expose portions of the source and drain regions are created. The via openings are filled with polysilicon interconnects, appropriately doped for low resistance contacts. Where the contact includes a resistor load, the polysilicon is not doped. Thus, the prior art approach of providing doped and undoped regions along the same polysilicon interconnect is not employed. Rather, the doped and undoped regions are physically separated. Consequently, the minimum length of the poly load is limited only by the ability to form via openings of small dimensions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.