Method of fabricating a MOSFET with graded source and drain regions

US4728617A · kind A · utility

Assignee

• Intel Corporation · US

Inventors

• Been-Jon Woo · Saratoga, US
• Mark A. Holler · Palo Alto, US
• Ender Hokelek · Santa Clara, US
• Sandra S. Lee · Los Altos, US

Key dates

• Filing date: Nov 4, 1986
• Grant date: Mar 1, 1988
• Expiry date: Nov 4, 2006

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/965

Abstract

A method of forming metal oxide semiconductor field-effect transistors (MOSFET) is described wherein the source and drain regions are disposed by ion implantation in a manner substantially perpendicular to the substrate surface in two steps, such that the concentration of impurities increases with lateral distance away from the gate electrode member to suppress the hot e injection, to prevent channeling effect, to increase punch through voltage and to increase gate-aided breakdown voltage.