Process for producing memory cell having stacked capacitor
US4742018A · kind A · utility
109Cited by
1References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 1, 1986 |
| Grant date | May 3, 1988 |
| Priority date | — |
| Expiry date | Dec 1, 2006 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/014
Abstract
A process for producing a memory cell having a stacked capacitor. As the reduction in device size of memory cells progresses, it becomes difficult to obtain a satisfactorily large capacitance even with a stacked capacitor structure. To enable a larger capacitance to be obtained for the same occupied area, projections and recesses are provided on the surface of a capacitor electrode. It is possible, according to the process, to readily produce projections and recesses for increasing the storage capacitance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.