Dram with FET stacked over capacitor
US4751557A · kind A · utility
42Cited by
17References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 8, 1986 |
| Grant date | Jun 14, 1988 |
| Priority date | — |
| Expiry date | Sep 8, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/395
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory wherein a part of each capacitor is formed on side walls of an island region surrounded with a recess formed in a semiconductor substrate, and the island region and other regions are electrically isolated by the recess.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.