Writing speed in multi-port static rams
US4764899A · kind A · utility
12Cited by
7References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 7, 1986 |
| Grant date | Aug 16, 1988 |
| Priority date | — |
| Expiry date | Feb 7, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A write-bias gate in the form of an FET is provided for each of the bit-lines. Each FET has its drain electrode connected to logic 1 and its source electrode connected to the bit-line. When one port is writing, the write-bias gates on the other port(s) are driven by a signal which causes them to enter a pass condition, supplying extra current to pull up the bit lines of the non-writing port(s).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.