Self-aligned process for fabricating small DMOS cells
US4774198A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 1987 |
| Grant date | Sep 27, 1988 |
| Priority date | — |
| Expiry date | Feb 26, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/393
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved fabrication process for vertical DMOS cells contemplates the prior definition of the gate areas by placing a polycrystalline silicon gate electrode and utilizing the gate electrode itself as a mask for implanting and diffusing the body regions, while forming the short region is carried out using self-alignment techniques which permit an easy control of the lateral extention of the region itself. A noncritical mask defines the zone where the short circuiting contact between the source electrode and the source and body regions in the middle of the DMOS cell will be made, also allowing the forming the source region. Opening of the relative contact is also effected by a self alignment technique, further simplifying the process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.