Method for successive alignment of chip patterns on a substrate
US4780617A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 1986 |
| Grant date | Oct 25, 1988 |
| Priority date | — |
| Expiry date | Oct 3, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/70425
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method for successive alignment of each of a plurality of chip patterns regularly arranged on a substrate to a reference position comprises moving the substrate so as to successively make selected chip patterns correspond to the reference position in accordance with design data representative of the positions of the selected chip patterns, measuring the positions of the selected chip patterns when made to correspond to the reference position, determining on the basis of the measured positions, coefficients of an operational equation so that the sum of the square of deviations between positions of the selected chip patterns determined by use of the operational equation and positions of the selected chip patterns represented by design data may be minimum, determining positions corresponding to the plurality of chip patterns on the basis of the operational equation, and moving the substrate in accordance with the determined positions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.