Interface system for interfacing a device tester to a device under test
US4795977A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 1987 |
| Grant date | Jan 3, 1989 |
| Priority date | — |
| Expiry date | Mar 19, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R1/07342
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A device tester, such as a memory tester, is electrically interfaced to a device under test, such as a memory die, by means of an improved interface system. The interface system includes an array of coaxial cables for making electrical connection to the test circuits of the device tester by means of coaxial connections at the tester ends. The coaxial cables are fitted at their other ends with slidable two-conductor connector receptacles which make connections to fixed male pins of spring loaded feedthrough connectors passing through a mother board. The spring loaced pins of the feedthroughs make electrical contact to eyelets terminals of strip-line circuits on a probe card (daughter board) terminating on an array of flexible probes for probing the memory die under test. As an alternative, the eyelet terminals of the daughter board are connected to sockets to receive the device under test. The electrical circuits of the interface system, including connectors, are dimensioned for impedance maching to reduce unwanted reflection of test signasl to extend the test frequency response up to the 1 to 2 GHz range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.