Semiconductor memory having selectively activated blocks including CMOS sense amplifiers
US4796234A · kind A · utility
34Cited by
3References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 5, 1986 |
| Grant date | Jan 3, 1989 |
| Priority date | — |
| Expiry date | Nov 5, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4091
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
It is contemplated to realize a semiconductor memory with a large memory capacity, high in integration and low in power dissipation. A semiconductor memory is disclosed, comprising a plurality of blocks each having a memory cell array and sense amplifier(s) to differentially amplify signals read out from the array, wherein a common driving line of amplifiers composed of N-channel MOS transistors among said sense amplifiers and a common driving line of amplifiers composed of P-channel MOS transistors among the sense amplifers are connected between different blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.