Self-limiting erase scheme for EEPROM
US4797856A · kind A · utility
53Cited by
4References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 16, 1987 |
| Grant date | Jan 10, 1989 |
| Priority date | — |
| Expiry date | Apr 16, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3472
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A self-limiting scheme to prevent an over-erase condition of a one-transistor EEPROM cell. During an erase cycle, a drain voltage is fed back to a floating gate to counteract a positive erase voltage on the source of the memory cell and therein reduce the electric field across the tunnel oxide leading to the cessation of erase. In another scheme, the drain voltage is fed back to deactivate the erase voltage when a predetermined drain voltage value is exceeded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.