Programmable I/O sequencer for use in an I/O processor

US4803622A · kind A · utility

Assignee

• Intel Corporation · US

Inventors

• William L. Bain, Jr. · Bellevue, US
• Robert Bedichek · Palo Alto, US
• George W. Cox · Terrace Park, US
• Gerhard Grassl · Grafing, DE
• Craig B. Peterson · Portland, US
• Justin R. Rattner · Beaverton, US
• Gurbir Singh · Gig Harbor, US
• John L. Wipfli · Hillsboro, US

Key dates

• Filing date: May 7, 1987
• Grant date: Feb 7, 1989
• Expiry date: May 7, 2007

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F13/124
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An I/O bus sequencer for providing a data path between an execution Unit (EU-10), a register file (14) and devices connected to a bus (28). A programmable logic array (PLA-18) stores a program which controls a service table (20). The service table includes a plurality of entries divided into fields. One of the fields when decoded instructs the PLA as to what kind of operation the bus sequencer is to perform. Line selection (priority) logic (22) connected to I/O request lines (30) and to the service table (20) determines which service table entry the PLA is to use. A bus interface connected to the I/O bus ports (26) and to the PLA (18) routes data between the I/O bus ports (26) and the register file (14), entries of which are controlled by use of register sets. The service table fields include register set descriptors for storing the status of register set buffers. The PLA decodes an ACCESS instruction to start an operation by loading the first register set descriptor, and then decodes sequential SUPPLY instructions to the entry. Each SUPPLY instruction loads an empty register set descriptor field to be used when the current register set descriptor field is exhausted.