Stacked static random access memory cell having capacitor
US4805147A · kind A · utility
41Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 9, 1986 |
| Grant date | Feb 14, 1989 |
| Priority date | — |
| Expiry date | Jun 9, 2006 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/906
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static random access memory cell in which capacitors are electrically connected to storage nodes, so that the memory cell will not suffer from soft error even when it is hit by alpha particles. The memory cell has MOS transistors, capacitors constituted by two polycrystalline silicon layers, and resistors constituted by a polycrystalline silicon layer, that are formed on a semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.