Dynamic RAM device having a separate test mode capability
US4811299A · kind A · utility
51Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 22, 1987 |
| Grant date | Mar 7, 1989 |
| Priority date | — |
| Expiry date | Apr 22, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31701
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed is a dynamic RAM device capable of initiating and cancelling the test mode in response to the combinations of the row address and column address strobe signals with the write enable signal, which combinations are left unused in the normal operating mode, instead of increasing the number of external control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.