Method of making a high performance MOS device having LDD regions with graded junctions
US4818714A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 2, 1987 |
| Grant date | Apr 4, 1989 |
| Priority date | — |
| Expiry date | Dec 2, 2007 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/90
Abstract
An MOS structure and a method for making same, including the formation of el-shaped shielding members used to form one or more lightly doped drain regions to avoid short channel and punch-through problems is disclosed which comprises forming a shielding layer of an insulating material over a gate electrode on a substrate; forming another layer of a dissimilar material over the shielding layer; anisotropically etching the layer of dissimilar material to form spacer portions adjacent the sidewalls of the gate electrode; removing the portions of the shielding layer not masked by the spacer portions, leaving one or more el-shaped shielding members; removing the spacer portions; N+ or P+ implanting the substrate at a sufficiently low energy to prevent penetration of the dopant through the el-shaped shielding member to form a highly doped source/drain region in the substrate not shielded by the el-shaped shielding member or the gate electrode; N- or P- implanting the substrate at a sufficiently high energy to penetrate through the el-shaped shielding member to form a lightly doped source/drain region in the portion of the substrate adjacent the P+ or N+ source/drain regions and separatin…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.