Jacob D. Haskell
34Patents
19h-index
10Co-inventors
78Inventor score
Filing activity: Jun 14, 1983 → Oct 4, 2007
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6297170A | Sacrificial multilayer anti-reflective coating for mos gate formation | Electricity | 205 | Expired |
| US6512263B1 | Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming | Physics | 182 | Expired |
| US4818714A | Method of making a high performance MOS device having LDD regions with graded junctions | Emerging Cross-Sectional Technologies | 74 | Expired |
| US5776821A | Method for forming a reduced width gate electrode | Electricity | 69 | Expired |
| US4495025A | Process for forming grooves having different depths using a single masking step | Electricity | 56 | Expired |
| US4954459A | Method of planarization of topologies in integrated circuit structures | Emerging Cross-Sectional Technologies | 55 | Expired |
| US4516316A | Method of making improved twin wells for CMOS devices by controlling spatial separation | Emerging Cross-Sectional Technologies | 38 | Expired |
| US4677589A | Dynamic random access memory cell having a charge amplifier | Physics | 33 | Expired |
| US4962064A | Method of planarization of topologies in integrated circuit structures | Emerging Cross-Sectional Technologies | 32 | Expired |
| US4729001A | Short-channel field effect transistor | Electricity | 32 | Expired |
| US5081516A | Self-aligned, planarized contacts for semiconductor devices | Electricity | 27 | Expired |
| US6133635A | Process for making self-aligned conductive via structures | Electricity | 23 | Expired |
| US4977108A | Method of making self-aligned, planarized contacts for semiconductor devices | Emerging Cross-Sectional Technologies | 23 | Expired |
| US5028555A | Self-aligned semiconductor devices | Emerging Cross-Sectional Technologies | 23 | Expired |
| US4964143A | EPROM element employing self-aligning process | Electricity | 22 | Expired |
| US4974055A | Self-aligned interconnects for semiconductor devices | Electricity | 21 | Expired |
| US5055427A | Process of forming self-aligned interconnects for semiconductor devices | Electricity | 20 | Expired |
| US5057902A | Self-aligned semiconductor devices | Electricity | 20 | Expired |
| US5091326A | EPROM element employing self-aligning process | Electricity | 19 | Expired |
| US4609934A | Semiconductor device having grooves of different depths for improved device isolation | Electricity | 15 | Expired |
| US5116778A | Dopant sources for CMOS device | Electricity | 14 | Expired |
| US6723604B2 | Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming | Physics | 12 | Expired |
| US5395796A | Etch stop layer using polymers for integrated circuits | Emerging Cross-Sectional Technologies | 11 | Expired |
| US6953964B2 | Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming | Physics | 10 | Expired |
| US4686559A | Topside sealing of integrated circuit device | Electricity | 8 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.