Semiconductor memory device having increased capacitance for the storing nodes of the memory cells
US4849801A · kind A · utility
30Cited by
5References
2Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 27, 1987 |
| Grant date | Jul 18, 1989 |
| Priority date | — |
| Expiry date | Oct 27, 2007 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
Abstract
A semiconductor memory device is provided in which an electrode applied with the power supply voltage or the ground voltage is provided on an insulating layer over the drain and/or the gate of the MOS transistors constituting the memory cell of a static memory device, thereby to increasing the capacitance of the storing node of the memory cell. This semiconductor memory device significantly reduces the occurrence of soft errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.